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**Asynchronous Counters:**

In the previous Counter tutorial we saw that **Asynchronous counters** can have 2^{n-1} counting states. But it is also possible to construct special counters with states less than their maximum output number by forcing the counter to reset itself to zero at a pre-determined value and these are called "truncated sequences".

If we take the modulo-16 ripple counter and modified it with additional logic gates it can be made to give a decade (divide-by-10) counter output for use in standard decimal counting and arithmetic circuits. Such counters are generally referred to as **Decade Counters**. A decade counter requires resetting to zero when the output count reaches the decimal value of 10, ie. when DCBA = 1010 and feed this back to the reset input. A counter with a count sequence from binary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD Decade counter because its ten state sequence is that of a BCD code but binary decade counters are also available.

**Asynchronous Decade (decimal 10) Counter:**

This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from "0000" until it reaches an output "1010" (decimal 10). Both outputs QB and QDare now equal to logic "1" and the output from the NAND gate changes state from logic "1" to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all theJ-K Flip-flops. This causes all of the Q outputs to be reset back to binary "0000" on the count of 10. Once QB and QD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the counter restarts again from "0000". We now have a decade or **Modulo-10** counter.

Clock Count |
Output bit Pattern | Decimal Value |
|||

QD | QC | QB | QA | ||

1 | 0 | 0 | 0 | 0 | 0 |

2 | 0 | 0 | 0 | 1 | 1 |

3 | 0 | 0 | 1 | 0 | 2 |

4 | 0 | 0 | 1 | 1 | 3 |

5 | 0 | 1 | 0 | 0 | 4 |

6 | 0 | 1 | 0 | 1 | 5 |

7 | 0 | 1 | 1 | 0 | 6 |

8 | 0 | 1 | 1 | 1 | 7 |

9 | 1 | 0 | 0 | 0 | 8 |

10 | 1 | 0 | 0 | 1 | 9 |

11 | Counter Resets its Outputs back to Zero |

Using the same idea of truncating counter output sequences, the above circuit could easily be adapted to other counting cycles be simply changing the connections to the AND gate. For example, a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to the AND gate from the outputs at "QC" and "QD", noting that the binary equivalent of 12 is "1100" and that output "QA" is the least significant bit (LSB).

Standard IC asynchronous counters are available are the TTL 74LS90 programmable ripple counter/divider which can be configured as a divide-by-2, divide-by-5 or any combination of both. The 74LS390 is a very flexible dual decade driver IC with a large number of "divide-by" combinations available ranging form 2, 4, 5, 10, 20, 25, 50, and 100.

**Asynchronous Counters:**

1. To understand the operation and characteristics of asynchronous counter designed with discrete gates .

2. To simulate and test a MOD-5 asynchronous counter using discrete gates

3. To simulate and test a MOD-6 asynchronous counter using discrete gates

**Procedure:**

1. Using the simulation software, draw and simulate the MOD-5 asynchronous counter shown below. Be sure to adjust the simulation speed so that the count can be observed both on the lights (Q0, Q1, & Q2) and the hex display.

2. Make the necessary modification to the MOD-5 asynchronous counter to make it a MOD-6 counter.

**Asynchronous Counters - Video:**

**Asynchronous Counters - Presentation:**