Modulo 5 Counter

A counter which is reset at the fifth clock pulse is called Mod 5 counter or Divide by 5 counter. The circuit diagram of Mod 5 counter is shown in the figure. This counter contains three JKMS flip-flop.


Logic Diagram:

Modulo 5 Counter.PNG

Truth table:

Clock
Qc
QB
QA
Reset
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
0
0
0
6
0
0
1


  • A 3 bit binary counter is normally counting from 000 to 111. The actual output of a 3 bit binary counter at the fifth clock pulse is 101.
  • A two input NAND gate is used to make a Mod 5 counter.
  • The outputs of the first and third flip flops (QA and QC) are connected to the input of the give NAND gate, and its output is connected to the RESET terminal of the counter,
  • Hence the counter is reset at the fifth clock pulse, which produces the output QC,QB,QA as 000. It is called divide by 5th counter or mod 5 counter.

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