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A timing diagram that illustrates the four different data transfer formats that are available with the SPI. This timing diagram illustrates a single 8 bit data transfer. The first thing you should notice in this timing diagram is that it is divided into three horizontal parts.
The first part describes the SCK and SSEL signals. The second part describes the MOSI and MISO signals when the CPHA variable is 0. The third part describes the MOSI and MISO signals when the CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated with CPOL set to both 0 and 1. The second point to note is the activation and de-activation of the SSEL signal. When CPHA = 0, the SSEL signal will always go inactive between data transfers. This is not guaranteed when CPHA = 1 (the signal can remain active).
The data and clock phase relationships are summarized in Table. This table summarizes the following for each setting of CPOL and CPHA.
SPI data to clock phase relationship
|CPOL||CPHA||First data driven||Other data driven||Data sampled|
|0||0||Prior to first SCK rising edge||SCK falling edge||SCK rising edge|
|0||1||First SCK rising edge||SCK rising edge||SCK falling edge|
|1||0||Prior to first SCK falling edge||SCK rising edge||SCK falling edge|
|1||1||First SCK falling edge||SCK falling edge||SCK rising edge|
The definition of when an 8 bit transfer starts and stops is dependent on whether a device is a master or a slave, and the setting of the CPHA variable. When a device is a master, the start of a transfer is indicated by the master having a byte of data that is ready to be transmitted.
At this point, the master can activate the clock, and begin the transfer. The transfer ends when the last clock cycle of the transfer is complete. When a device is a slave, and CPHA is set to 0, the transfer starts when the SSEL signal goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on the last clock edge where data is sampled.