|
UStudy aims to provide Educational Content for Polytechnic College students based on the latest K Scheme syllabus of Tamil Nadu. |
SSP Register Map
| Name | Description | Access |
Reset value | Address |
| SSPCR0 | Control Register 0. Selects the serial clock rate, bus type, and data size. |
R/W | 0x0000 | 0xE006 8000 |
| SSPCR1 | Control Register 1. Selects master/slave and other modes. |
R/W | 0x00 | 0xE006 8004 |
| SSPDR | Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. |
R/W | 0x0000 | 0xE006 8008 |
| SSPSR | Status Register | RO | 0x03 | 0xE006 800C |
| SSPCPSR | Clock Prescale Register | R/W | 0x00 | 0xE006 8010 |
| SSPIMSC | Interrupt Mask Set and Clear Register | R/W | 0x00 | 0xE006 8014 |
| SSPRIS | Raw Interrupt Status Register | R/W | 0x04 | 0xE006 8018 |
| SSPMIS | Masked Interrupt Status Register | RO | 0x00 | 0xE006 801C |
| SSPICR | SSPICR Interrupt Clear Register | WO | NA | 0xE006 8020 |
